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preliminary product information t h i s d o cume n t c on t ai n s i nf o rm a ti o n f o r a n ew p rod u ct. ci r ru s lo g ic reserves th e ri g ht t o mod i fy th i s p ro d uc t wit h ou t no t ic e . 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs7620 ccd imager analog processor features l 13-bit a/d conversion using drx? technology l backlight compensation l supports t hree inpu t ranges of 0.53v, 1.07v, and 1 . 60v l multi-sync ccd timing generator l high resolution output mode l low resolution (preview) output mode for l c d d r iver l integrated correlated double sampler l digital black level clamp l digital outputs se l ectable for 13, 12, or 10 bits l two integra t ed general p urpose d a cs l low power consumpt i on l power down mode l high speed ser i al interface l supports a large varie t y o f clock input frequencies l low power mode opt i on description the c s7 6 20 is a low-po w er an a log fron t - e nd p r o c e ssor for in t erlin e or fr a me tra n sf e r ccd ima g ers. m ain a ppli- c a ti o ns i ncl u d e d i gi t a l sti l l i ma g e ca m eras w ith u p t o 8 k 8 k pi x e l s. the architecture inclu d es a c o rrelat e d do u ble s a mpler, black level cl a mp and a 13-bi t a/d c o nversion m o dule usi n g pat e nted d r x techn o l o gy. in a dditi o n , the chip c o nt a ins a timing g e nerat o r, which su p ports c o mm o n ccds f r o m ib m , a n d pol a r o id. fo r ccds u sin g differe n t ti m i n g sig n als, t h e i n ternal ti m i n g ge n erat o r can b e bypassed. there a re 2 ge n eral p urpose dacs a v a ilable which c a n b e used t o driv e mot o rs f o r iris a n d sh u tter contr o l. chip para m eters can b e p r o gram m ed usi n g a hi g h s p eed 4-wire asy n c h r o no u s d i g ital interf a c e . th e chip o utp u ts d igitized c c d d at a in eit h er 1 3-bit , 12- bit o r 10-bi t forma t . 1 0-bit o u tpu t s ar e gen e rated from t h e 13- b it a/d out p ut by a pro g r a mm a ble c o mp a nding curv e . orde r ing information cs762 0 -iq -40 t o +85 c 6 4 - p i n tqfp 10x1 0 x 1 .4 m m ccd out p ut m as t er cd s / d r x da t a o u t p l l output register serial block compan d er a/d con v er t er black le v el t i m i ng g e nera t or ccd t iming signals clock out gain clock in t er f ace s e r i a l bus dac 2 dacs ou t p u t s clock jul 9 9 ds30 1 pp2
cs7620 2 ds301pp2 table of contents 1 characteristics/specifications .................................................................................. 5 digital characteristics ................................................................................................. 5 power consumption ........................................................................................................ 5 recommended operating characteristics............................................................ 5 absolute maximum ratings ........................................................................................... 6 adc (analog-to-digital converter) ........................................................................... 6 cds/vga parameters ........................................................................................................ 6 frequency synthesizer parameters ....................................................................... 6 serial interface timing specifications ................................................................... 7 2 general description ........................................................................................................ 8 3 operation .................................................................................................................. ............ 9 3.1 black level adjustment .................................................................................................... 10 3.2 gain adjust block ......................................................................................................... .... 12 3.3 13-to-10 bit compander ................................................................................................... 1 3 3.4 timing generator .......................................................................................................... ... 15 3.4.1 vertical and horizontal timing mode .................................................................. 15 3.4.2 horizontal only timing mode .............................................................................. 16 3.4.3 slave mode ......................................................................................................... 17 3.4.4 horizontal timing generator ............................................................................... 17 3.4.5 vertical timing generator ................................................................................... 19 3.4.6 frame timing ...................................................................................................... 19 3.5 frequency synthesizer .................................................................................................... 1 9 3.6 8-bit general purpose dacs ........................................................................................... 20 3.7 stand by mode ............................................................................................................. ... 20 3.8 preview mode .............................................................................................................. .... 21 3.9 serial interface .......................................................................................................... ....... 21 3.10 recommended register settings .................................................................................. 21 4 register descriptions ................................................................................................... 25 4.1 reset ...................................................................................................................... .......... 28 4.2 power down control 1 ...................................................................................................... 2 8 4.3 power down control 2 ...................................................................................................... 2 9 4.4 operation control 1........................................................................................................ ... 29 4.5 operation control 2........................................................................................................ ... 31 4.6 black level control - accumulator (lsb).......................................................................... 32 4.7 black level control - accumulator (msb)......................................................................... 32 4.8 general black level........................................................................................................ .. 33 4.9 black level control - loop gain, clamp length............................................................... 33 4.10 gain calibration - offset 1 .............................................................................................. 3 4 4.11 gain calibration - offset 2 .............................................................................................. 3 4 4.12 gain calibration - offset 3 .............................................................................................. 3 5 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs7620 ds301pp2 3 4.13 timing control - number of lines (msbs)...................................................................... 36 4.14 timing control - number of lines (lsbs)....................................................................... 38 4.15 timing control - number of columns (msbs) ................................................................ 38 4.16 timing control - number of columns (lsbs) ................................................................. 39 4.17 timing control - number of dark rows.......................................................................... 39 4.18 timing control - start of black pixels ............................................................................. 40 4.19 timing control - end of black pixels .............................................................................. 40 4.20 timing control - number of rows until active ................................................................ 41 4.21 timing control - start of active pixels ............................................................................ 42 4.22 timing control - vertical time division .......................................................................... 42 4.23 timing control - lines in storage buffer (msbs) ........................................................... 43 4.24 timing control - lines in storage buffer (lsbs) ............................................................ 43 4.25 timing control - extra lines of exposure in low resolution mode (msbs) .................. 43 4.26 timing control - extra lines of exposure in low resolution mode (lsbs) ................... 44 4.27 timing control - vsync mode, lines of exposure in low resolution mode (msbs) ...... 44 4.28 timing control - lines of exposure in low resolution mode (msbs) ............................ 47 4.29 timing control - polarity of vertical shift outputs .......................................................... 47 4.30 horizontal timing control - h1 ....................................................................................... 48 4.31 horizontal timing control - h2 ....................................................................................... 49 4.32 horizontal timing control - h3 ....................................................................................... 50 4.33 horizontal timing control - h4 ....................................................................................... 51 4.34 horizontal timing control - analog delays..................................................................... 52 4.35 compander - black slope, slopes (msbs)..................................................................... 53 4.36 compander - slope 1 (lsbs) ......................................................................................... 53 4.37 compander - slope 2 (lsbs) ......................................................................................... 54 4.38 compander - slope 3 (lsbs) ......................................................................................... 54 4.39 compander - slope 4 (lsbs) ......................................................................................... 55 4.40 compander - offset 1 ..................................................................................................... 5 5 4.41 compander - offsets (msbs) ......................................................................................... 56 4.42 compander - offset 2 (lsbs) ......................................................................................... 56 4.43 compander - offset 3 (lsbs) ......................................................................................... 57 4.44 compander - offset 4 (lsbs) ......................................................................................... 57 4.45 compander - x1 (msbs) ................................................................................................ 58 4.46 compander - x1 (lsbs) ................................................................................................. 58 4.47 compander - x2 (msbs) ................................................................................................ 59 4.48 compander - x2 (lsbs) ................................................................................................. 59 4.49 compander - x3 (msbs) ................................................................................................ 60 4.50 compander - x3 (lsbs) ................................................................................................. 60 4.51 power_up counter.......................................................................................................... 61 4.52 valid_data/dout edge/clock_in divider.......................................................................... 61 4.53 dac #1 control ............................................................................................................ .. 62 4.54 dac #2 control ............................................................................................................ .. 62 4.55 device id ................................................................................................................. ....... 63 4.56 rev code.................................................................................................................. ...... 63 5 pin descriptions ........................................................................................................... .... 64 5.1 supply .................................................................................................................... .......... 65 5.2 ground .................................................................................................................... ......... 65 5.3 cmos input ................................................................................................................ ..... 65 5.4 cmos analog input ......................................................................................................... 66 5.5 cmos analog output ...................................................................................................... 66 5.6 cmos 4 ma output ......................................................................................................... 6 6 5.7 cmos 28 ma output ....................................................................................................... 67 5.8 misc ...................................................................................................................... ........... 67 6 package dimensions ....................................................................................................... 68
cs7620 4 ds301pp2 list of figures figure 1. sen timing ........................................................................................................... .............. 7 figure 2. serial write timing.................................................................................................. ............ 7 figure 3. read data timing ..................................................................................................... .......... 7 figure 4. digital camera block diagram ......................................................................................... ... 8 figure 5. cs7620 block diagram................................................................................................. ...... 8 figure 6. idealized ccd output waveform ........................................................................................ .9 figure 7. transfer function of vga circuit (assuming full scale level of 1.07v)................................ 10 figure 8. block diagram of cds/vga circuit.................................................................................... 1 0 figure 9. idealized timing diagram of vga/cds circuit.................................................................... 11 figure 10. black level adjustment loop......................................................................................... .... 11 figure 11. transfer function of vin to gain adjust output block (assuming full scale level of 1.07v)13 figure 12. gain adjust output block............................................................................................ ..... 13 figure 13. 13-to-10 bit compander .............................................................................................. ..... 15 figure 14. cs7620 output data and clocks ...................................................................................... 1 5 figure 15. cs7620 output data and clocks ...................................................................................... 1 6 figure 16. picture signal timing ............................................................................................... ....... 16 figure 17. signal timing for horizontal only mode.......................................................................... 17 figure 18. signal timing for slave mode ........................................................................................ .17 figure 19. detailed signal timing showing internal clock phases ................................................. 18 figure 20. default timing of horizontal signals to the ccd ............................................................ 18 figure 21. high resolution mode................................................................................................ ..... 20 figure 22. low resolution mode................................................................................................. ..... 20 figure 23. typical connection diagram using vertical and horizontal timing mode...................... 22 figure 24. typical connection diagram using horizontal only timing mode ................................. 23 figure 25. typical connection diagram using slave mode............................................................. 24 figure 26. transfer function of analog input to digital output (assuming full scale level of 1.07v) 36 figure 27. transfer function of adc with fixed gain settings (assuming full scale level of 1.07v) 37 figure 28. typical ccd pixel arrangement ..................................................................................... 41 figure 29. 2 million pixel ibm ccd (5:1 reduction) .......................................................................... 46 figure 30. 2 million pixel ibm ccd (5:1 reduction) rgb pattern ..................................................... 46 figure 31. 1.3 million pixel ibm ccd (8:2 reduction) ....................................................................... 46 figure 32. 1.3 million pixel ibm ccd (4:1 reduction) rgb pattern .................................................. 46 figure 33. vertical timing division for low resolution mode .......................................................... 46 list of tables table 1. companding operational control....................................................................................... 1 4 table 2. default phases for horizontal signal edges ...................................................................... 18 table 3. different resolution operating modes ............................................................................... 19 table 4. general purpose dac specifications ................................................................................. 20 table 5. ibm35ccd2pix1 ......................................................................................................... ...... 25 table 6. ibm35ccd13pix ......................................................................................................... ...... 25 table 7. register description .................................................................................................. ......... 25 table 8. different resolution operating modes ............................................................................... 30 table 9. full scale level choices .............................................................................................. ...... 32 table 10. offset range ......................................................................................................... ........... 32 table 11. black loop time constant ............................................................................................. .. 33
cs7620 ds301pp2 5 1 characteristics/specifications digital characteristics (t a = 25 c; v dd _ring = 5 v) power consumption (t a = 25 c; v aa = v dd = 5 v; output load = 30 pf) recommended operating characteristics parameter symbol min typ max units logic inputs high-level input voltage v ih v dd _ring-0.8 - - v low-level input voltage v il --0.8v input leakage current i in --10 m a logic outputs high-level output source current @ i oh = 4ma v oh v dd -0.4 - v low-level output sink current @ i ol = 4ma v ol --0.4v (h1-h4) output source current @ i oh = 24ma v oh_hclk v dd -0.4 v (h1-h4) output sink current @ i ol = 24 ma v ol_hclk 0.4 v 3-state leakage current i oz --10 m a parameter symbol min typ max units power dissipation peak mode preview mode stand by down p d p dlr p dpd - - - 375 275 0.125 - - - mw mw mw analog power supply current peak mode preview mode stand by down i an i alr i apd - - - 60 40 0.025 - - - ma ma ma digital power supply current peak/preview mode stand by mode i dn i dpd - - 15 0 - - ma ma parameter symbol min typ max units power supply voltage v aa1 , v aa2 , v ddd 4.5 5.0 5.5 v power supply voltage for digital pads v dd_ring 3.0 3.3/5.0 5.5 v power supply voltage for horizontal ccd signal outputs v aa3 3.0 3.3/5.0 5.5 v gnda to gndd voltage differential 10 mv clock frequency range 8 160 mhz analog full scale input voltage range (w/ fs_lvl = 10) (w/ fs_lvl = 01) (w/ fs_lvl = 00) a in -1.60 1.07 0.53 -v p-p
cs7620 6 ds301pp2 absolute maximum ratings warning: warning:operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. adc (analog-to-digital converter) cds/vga parameters frequency synthesizer parameters parameter symbol min max units power supply voltage v aa1 , v aa2 , v aa3 , v dd_ring , v ddd -0.3 7.0 v digital input voltage gndd-0.3 v ddd +0.3 v analog input voltage a in gnda-0.3 v aai +0.3 v input current (except supply pins) 10 ma ambient temperature range 70 +70 c lead solder temperature (10sec duration) +260 c storage temperature range -65 +150 c parameter symbol min typ max unit input voltage range (w/ fs_lvl = 10) (w/ fs_lvl = 01) (w/ fs_lvl = 00) -1.60 1.07 .53 -v 0-p adc resolution - 10 - bits conversion rate maximum 16 - - mhz total differential non-linearity - 1 - lsb total integral non-linearity - 1 - lsb parameter symbol min typ max unit input voltage range (w/ fs_lvl = 10) (w/ fs_lvl = 01) (w/ fs_lvl = 00) -1.60 1.07 .53 -v 0-p total gain range a vga - 18 - db input referred noise (rms) maximum gain setting vn vga -- 0.2 mv parameter symbol min typ max unit clkin frequency f clock_in 8 - 160 mhz pll output frequency f pll_out 8 - 16 mhz clkin duty cycle d clock_in 20 - 80 % output jitter - 200 - ps duty cycle - 50 - % pll acquisition time - 200 - s
cs7620 ds301pp2 7 serial interface timing specifications notes: 1. the minimum serial clock period must be longer than two pixel clock periods. description symbol minimum maximum unit enable setup t1 10 - ns sdat setup t2 10 - ns sdat hold t3 10 - ns serial clock period (note 1) t4 143 - ns write data invalid t5 0 10 ns read data valid t6 0 10 ns clock to disable t7 143 - ns sen rise to sen fall t8 200 - ns figure 1. sen timing sclk sdati r/w , addr <6.0> data <7.0> t7 t8 t1 sen figure 2. serial write timing sdati t4 sclk sen t2 t3 r/w a6 a5 a6 a3 figure 3. read data timing sclk a0 xx (dont care) sdati t5 t6 d7 d6 d5 sdato
cs7620 8 ds301pp2 2 general description the cs7620 forms the heart of a four chip digital ccd camera. the four chips include the ccd im- ager, the cs7620 ccd digitizer, a vertical drive in- terface chip and a backend dsp chip to further process the digital data (see figure 4.) the cs7620 has a built-in timing generator which works with imagers from ibm and polaroid. if other ccds are used, the internal timing generator can be bypassed and replaced by an external device, which outputs the appropriate timing signals. the patented drx technology allows the cs7620 to output data with 13-bit dynamic range, and at the same time reducing the power consumption to a 10- bit equivalent a/d converter. the digitized output is either available in 13-bits, 12-bits or 10-bits. the 10-bit output is created by companding the 13-bit a/d output to 10-bits. the companding curve consists of 4 linear segments, where each slope and each start point is user pro- grammable. two output control signals and one output clock provide synchronization with the out- put data. a block diagram of the cs7620 chip is shown in figure 5. ccd vertical drive dc-dc converter backend dsp lcd panel video output +5 v +5 v to -5 v cds/adc timing control cs7620 figure 4. digital camera block diagram ain rg h1 h2 h3 h4 clock_in bypass_pll diag[1:0] dac_out1 dac_out2 sen sdati sdato sclk v1 v2 v3 v4 s1 s2 s3 s4 rd_out hsync expose line_ena bg_res ref_capn ref_capp test rst pwr_dn scan_mode clamp clko dout[12:0] (up to 3 may be unused) gnd[5] vdd[5] s cds/vga a/d gain adjust 13 to 10-bit compander m u x black level analog clock generator pll dac1 dac2 serial interface timing generator reference 1 f 10 k w figure 5. cs7620 block diagram
cs7620 ds301pp2 9 3operation cds/vga (correlated double sampling/vari- able gain amplification) an idealized waveform of the ccd output is shown in figure 6. the ccd output contains reset noise, thermal noise, and 1/f noise generated in the ccd output circuit. this degrades the s/n ratio and must be cancelled. since the noise during the active video portion of the ccd signal is assumed to be corre- lated with the noise during the feed through portion of the signal, this noise can be cancelled by sub- tracting the feed through level from the video level. this operation is called correlated double sam- pling. the active video signal is the difference be- tween the feed through and video levels. the active video signal varies according to light conditions. in order to insure that the full dynamic range of the adc is utilized even under low light conditions, the ccd output is amplified using a vga. the gain control is provided by a 2 bit control word generated by an adc after stage 1, which has a gain of 1. based on the input voltage, a gain of 1x, 2x, 4x, or 8x is subsequently applied to the signal. the amount of gain is later adjusted in the digital section. after the vga, the signal gets digitized by a 10 bit adc. the 2 bit adc output is used in combination with the 10 bit adc output to produce a 13 bit output. adding more gain before the adc does not offer performance improvement because the noise of the ccd (after gain is applied to it) begins to dominate over the quantization noise. any additional gain should be done in digital since the performance is the same as when the adc output has the addition- al gain applied. in order to add more flexibility, the full scale input range is programmable through register 07h. this setting will determine what input level maps to the highest adc output code. thus depending on the saturation level of the particular ccd used in the system, an appropriate full scale input level can be chosen in the cs7620. the choices of full scale in- put level are 1.6v, 1.07v, 0.53v with 1.07v the default. in the remainder of this document, all the figures and discussions assume a full scale level of 1.07 is used. if a different full scale level is used, all the voltages scale up or down by x1.5 or x0.5 for 1.6v and 0.53v full scale levels respectively. the transfer function of the vga portion of the cir- cuit is shown in figure 7 with full scale level = 1.07. it is assumed that the cds has already been performed. if desired, the gain switching function- ality can be disabled and forced to a fixed gain of 8x, 4x, 2x, or 1x. this way any dynamic range en- hancement is lost and the digital output is only 10 bits. if a fixed gain of 1x is selected, dout[12:3] is used as the output, a fixed gain of 2x will use dout[11:2], etc. in order to use this mode, the reset level feed through level video level pixel period figure 6. idealized ccd output waveform dark max. brightness video range signal
cs7620 10 ds301pp2 fixed gain register (16h) should be set and the cali- bration offset registers (10h - 12h) should be set to 0. the cds/vga circuit is composed of three stages. the first stage has a fixed gain of 1, and the second and third stages have variable gain with a combined gain range of 1 to 8 (0-18 db). figure 8 shows a block diagram of the cds/vga circuit. the total gain is a = (c2/c3)(c4/c5) which is adjusted by varying c3 and c5. the capacitor cb on the front of stage 1 is for black level adjustment and will be discussed in detail later. this circuit utilizes a two phase non-overlapping clock to perform the desired cds function. the two phase clock also allows the video signal to be passed to the output while retaining a positive po- larity signal. figure 9 shows a timing diagram of the two phase clock along with the ccd signal and output signals of stages one, two and three. there is an internal mid-scale dc bias level circuit at the input pin. this allows ac coupling into the cs7620 with a capacitor and having the input auto- matically biased to mid-supply without worrying about external circuitry to perform this task. 3.1 black level adjustment in order to maintain a constant reference level for black pixels, a feedback loop is implemented that vout (v) vin (v) 1.07 0.53 0.27 0.13 1.07 0.5 1x 2x 4x 8x adc output 00 01 10 11 figure 7. transfer function of vga circuit (assuming full scale level of 1.07v) -a2 -a3 c2 c3 c4 c5 f 1 f 2 stage 2 stage 3 vout vo1 -a1 c1 c1 f 1 vin adc vo2 stage 1 controls c3, c5 controls gain adjust block in digital 2 cb vref to aout circuitry figure 8. block diagram of cds/vga circuit 100 k w 100 k w
cs7620 ds301pp2 11 sets the black level value at the output of the adc to 64 in the 13 bit digital code. this loop is active during the optically black pixels which are output at the beginning and end of a frame as well as dur- ing a portion of the horizontal blanking period. the presence of black pixels in the ccd output is indi- cated by the clamp pulse, which can either be supplied externally or generated internally if the timing for the ccd is generated by the cs7620. the black level can also be written to through the serial port. in order to acquire a starting value for the black lev- el, the loop will run over the several lines of black pixels at the beginning of the frame. the block di- agram of the loop is shown in figure 10. the up- date rate is once per line during active pixel lines, and once every (n + 10) pixels during the optical black lines. ccd input signal f 1 f 2 out of stage 1 out of stage 2 out of stage 3 figure 9. idealized timing diagram of vga/cds circuit v(1) v(2) v(3) v(1) v(2) v(3) v(1) v(2) v(3) v(1) v(2) adc z -1 + + 10 7 9 dac binary to therm z -1 f u f p f u = update frequency f p = pixel frequency k clip cds/vga s vin from serial interface mux + blk lvl loop 64 figure 10. black level adjustment loop - gain reg
cs7620 12 ds301pp2 the open-loop transfer function of the black level adjustment loop is blk_gain = 1, 2, 4, or 8 where blk_gain is programmable through a register and n = # of black pixels during clamp time, which is also programmable. the value of kxn will deter- mine the open-loop gain of the system. the settling time for the loop can be calculated using the fol- lowing formula: for offset range=1 (reg 06h, bit 0) for offset range =0 during fixed gain mode the time constant is a little different. in order to achieve no ringing in the settling use, for offset range = 1, and for offset range = 0. the 9 msbs of the black level accumulator can be read or written through a register. if written, the lsbs are set to zero. the black level is set to 8 in a 10-bit digital output representation. in a 13-bit representation, it is set to 64. the power-up de- fault value in the accumulator is at mid level. also note that the black level adjust loop can be disabled. in addition, the black level can be pro- grammed through the serial port. 3.2 gain adjust block in order to increase the dynamic range of the adc, a variable gain, whose value is determined by the signal level, is applied to each pixel. this allows for 13 bits of dynamic range and 10 bits of resolu- tion after accounting for the significance of the adc output bits. the gain applied in the analog is illustrated in the transfer curve in figure 7. once the signal is digitized, the gain adjust block uses the gain information for a given pixel word and shifts its bits accordingly. for example, using the default full scale level of 1.07v, if vin = 0.3 v, the vga would choose a gain of 2x so the adc input is 0.6 v. the 10-bit output of the adc (with no black level) is (0.6/1.07) 1024 = 574, or 1000111110. in binary. the gain adjust block will take this value for a fixed gain of 1: for a fixed gain of 2: hz () kn z1 C ------------- = k 1 256 -------- - blk_gain = t 1 1nk C () ln -------------------------- - C ? ?? 1 fu ---- - ? ?? = t 1 1 nk 2 ------- C ? ?? ln --------------------------- - C ? ? ? ? ?? 1 fu ---- - ? ?? = t 1 1 nk 8 ------- C ? ?? ln --------------------------- - C ? ? ? ? ?? 1 fu ---- - ? ?? = t 1 1 nk 4 ------- C ? ?? ln --------------------------- - C ? ? ? ? ?? 1 fu ---- - ? ?? = for a fixed gain of 4: for a fixed gain of 8: t 1 1 nk 2 ------- C ? ?? ln --------------------------- - C ? ? ? ? ?? 1 fu ---- - ? ?? = t 1 1nk C () ln -------------------------- - C ? ?? 1 fu ---- - ? ?? = n k --- - 1 n 2k ------- 1
cs7620 ds301pp2 13 plus the bits representing the 2x gain and divide the output by two (shift right by 1). the output of the gain adjust block is then 0100011111.000. note that the decimal point is virtual, having no exist- ence in silicon. it is representing the fact that we keep 3 extra bits of lower significance in the output. in the same manner, if vin = 0.75 v, a gain of 1x would be chosen and the output of the gain adjust block would be 1011001101000. the transfer function of the vin/gain adjust out is shown in figure 11. a block diagram of the gain adjust block is shown in figure 12. since the analog gain changes do not match the digital shifts exactly, there is a potential to have non-monotonic digital output. in order to remove this problem, calibration is performed. during cal- ibration, offset values are found that will be used to counteract the errors caused by the analog gain mismatch. using these offset values, the final out- put is a monotonic continuous 13-bit value. 3.3 13-to-10 bit compander while a 13 bit output may be useful in some appli- cations, others may require the standard 10 bit out- put. to accommodate this and yet still retain the advantages of the increased dynamic range, a 13- to-10 (or 13-to-12) bit compander is included. by dig adjust out (13 bits) vin (v) 1.07 0.53 0.27 0.13 8192 4096 1x 2x 4x 8x adc output 00 01 10 11 1024 2048 0 figure 11. transfer function of vin to gain adjust output block (assuming full scale level of 1.07v) gain adjust shift by 0,1,2, or 3 adc output 10 2 vga_adc output to digital gain 13 figure 12. gain adjust output block
cs7620 14 ds301pp2 using the picture content as a guide, the user can se- lect which curve will lead to the best overall dy- namic range in the picture. the companding module takes 13-bit data as input, and outputs ei- ther 10-bit companded data, 12-bit msb-clipped data or it lets the original 13-bit data pass through. by programming the compander in the way that is shown in figure 13, it is possible to compensate for backlighting conditions. details in dark areas stay visible, even in very complex lighting conditions. these three modes can be selected through 2 regis- ter bits in operational control. in the 12-bit clipped mode, any input above 4095 gets clipped to 4095. in the 10-bit companded mode, the input gets companded through a four segment, three knees, fully programmable curve. to program the curve, the placement of the three knees in the companding curve must be deter- mined. the next step is to determine the slope of the four segments created by the three knees (slope for each segment is defined as delta y / delta x). fi- nally, offsets must be calculated to keep the com- panding curve continuous. a fourth knee exists in the curve, which represents the black level value. there are two options for the 10-bit black value. in case one, a linear mapping is employed such that blacker-than-black pixel in- formation is kept, with black (code 64 in the 13 bit data) being defined as code 8 in the 10 bit domain. the second option clips all pixel values less than black (code 64 in the 13 bit data) to a programma- ble offset value, offset1. this may be set to 0 if de- sired. this option will lose the blacker-than- black pixel information, but allow for slightly more dynamic range. note: if using the linear mode (option 1), offset1 must be set to 8. registers x1 through x3 should be programmed with the x coordinates of each one of the three knees. registers slope1 through slope4 should be pro- grammed with 256 multiplied by the calculated slopes. finally, the offsets can be programmed following the formulas below: y1 = slope1/256 (x1-64) + offset1 y2 = slope2/256 (x2-x1) + y1 y3 = slope3/256 (x3-x2) + y2 offset2 = y1 - (x1 slope2 / 256) offset3 = y2 - (x2 slope3 / 256) offset4 = y3 - (x3 slope4 / 256) (use integer division and discard the remainder) when using the 10 bit companded output, be aware of the non-linearity of the output data. if linear out- put is needed to perform awb or agc, a linear curve can be implemented to gather statistics. this can be achieved by writing 8191 to x1 (set register 38h to 1fh and set register 39h to ffh) and setting slope1 to 32 (set register 2eh to 00010xxxb and set register 2fh to 20h). once the statistics have been gathered, all four registers should be returned to their previous values before taking the actual pic- ture. bits_out register bits output mode 0x 10 bits companded 10 13 bits 11 12 bits (clipped) table 1. companding operational control
cs7620 ds301pp2 15 the output of the compander is available at the pins dout<9:0> and it makes transitions either at the falling or rising edges of the pixel rate clock cl- ko, controlled by a register bit. the falling edge option is shown in figure 14. two options exist for outputting data. the first op- tion will output the pixel rate clock on the clko pin. the polarity of the pixel clock out of the pin is programmable so that the user may choose the ap- propriate clock edge to latch in the data. based on the rd_out and hsync signals, the user will be able to determine when he is over active pixels. the second option will output a data_valid signal on the clko pin that is synchronous with the input clock (figure 15). the data_valid signal will only toggle over active pixels. the user may then latch the data during this valid time. note: data_valid mode cannot be used if the system clock runs at the pixel rate. 3.4 timing generator there are three timing options available with the cs7620. the chip may produce all the vertical and horizontal timing for the imager, only the horizon- tal timing, or the chip may be used in a complete slave mode and not produce any of the ccd timing at all. each will be discussed in detail in this sec- tion. 3.4.1 vertical and horizontal timing mode to select this option, the user must tie the bypass_pll pin low and select the proper inter- nal timing mode in the timing mode register. the cs7620 is the master of the clocking. it will pro- vide vertical outputs and horizontal outputs. in this mode, the user must control two signals. the first is the master pwr_dn signal. when this signal is high, all of the cs7620 powers down except for the 1023 code_in code_out 8191 x1 x2 x3 slope1 slope2 slope3 slope4 offset2 offset3 offset4 offset1 64 (x2,y2) (x1,y1) (x3,y3) figure 13. 13-to-10 bit compander figure 14. cs7620 output data and clocks clko dout<9:0>
cs7620 16 ds301pp2 dac outputs (these may be powered down through register control if they are not being used). the sec- ond signal is the expose signal. this signal should go high at the beginning of exposure and low at the beginning of readout. the suggested tim- ing of these signals is shown in figure 16. note that the chip must power up at least 500 s before read- out begins. the line_ena and clamp pins are not used in this mode. 3.4.2 horizontal only timing mode to select this mode, the user must set the bypass_pll pin low and select external timing mode in the timing mode register. the cs7620 is the master of the pixel rate timing, but the line and frame timing is controlled externally. in this mode, the user must control four signals- pwr_dn, ex- pose, line_ena, and clamp. the master pwr_dn signal may be used to conserve power during non-readout time. the expose pin is rede- fined as the non-readout signal. when high, the h1-h4 and rg signals are set in their idle state (low for h1-h4, high for rg). the line-ena pin should be high during the vertical shift and load pe- riods. this will hold the h1-h4 signals in their user-programmable default states. the clamp pin should be high when over dark reference (black) pixels. the suggested timing for these sig- nals is shown in figure 17. note that the chip should power up at least 500 s before the begin- ning of readout. the clamp signal may also be high during the dark pixel lines at the beginning of the frame. figure 15. cs7620 output data and clocks clko (data_valid) dout<9:0> system_clk t frame t exp t readout expose signal figure 16. picture signal timing warning: note: it is recommended to keep the part in power down mode while not in use to reduce power powerdown signal >500 s
cs7620 ds301pp2 17 3.4.3 slave mode to select this mode, the user must set the bypass_pll pin high and select external timing mode in the timing register. the cs7620 timing is now slaved off of an external source and supplied with sampling clocks for feedthrough and data. in this mode, the user must control five signals- pwr_dn, expose, clamp, ck_ft (clock_in), and ck_dt (line_ena). the master pwr_dn signal may be used to conserve power during non-readout time. the expose pin is redefined as the non-readout signal. using the falling edge of this signal, the chip will delay its rd_out pin output by the appropriate amount as determined by the chip latency so that it will go ac- tive at the correct point in the data stream. clamp should be high when over the dark reference pixels. the clock_in and line_ena pins are rede- fined as the ck_ft and ck_dt signals, which sample the feedthrough and data levels, respective- ly. the suggested timing for pwr_dn, expose, and clamp is the same as shown previously in figures 16 and 17. the timing for ck_ft (clock-in) and ck_dt (line-ena) is shown in figure 18. 3.4.4 horizontal timing generator during every horizontal line period the data from the horizontal shift register is shifted out on the ccd output pin one pixel at a time. the analog tim- ing generator creates the required driving signals to control the ccd horizontal timing as well as the analog sampling signals. the timing signals in- volved in this operation are h1, h2, h3, h4 and rg. the exact timing of these signals can be con- t line clamp line_ena signal signal extended pixels dark pixels active v shift & load t line+1 figure 17. signal timing for horizontal only mode pixels active pixels v shift & load ccd input signal ck_dt ck_ft figure 18. signal timing for slave mode
cs7620 18 ds301pp2 trolled through the serial interface as described be- low. the pixel period is broken down into 8 equal time periods. by delaying the clock a given number of these time periods, different phases are created. this is shown in figure 19. these clock phases are labeled t0-t7 and are shown relative to an idealized ccd signal and the internal sampling signals. using these eight clock phases, the user may set the rising and falling edges of each horizontal pixel clock at 1/8 of a pixel clock period. in addition, the user may set each horizontal signal to a default state when the output lines are to be held constant during blanking. the default timing for the hori- zontal signals is shown in figure 20 and table 2. see the register listing for more details. ideal ccd signal ck_ft ck_dt internal sampling clocks figure 19. detailed signal timing showing internal clock phases h2 h3 h1 h4 rg t0 t4 t5 t6 t7 t0 t3 t4 t5 t6 t7 t1 t2 t3 t1 t2 ideal ccd signal default settings figure 20. default timing of horizontal signals to the ccd signal rising edge falling edge hold level h1 t0 t5 high (1) h2 t2 t7 high (1) h3 t4 t1 high (1) h4 t6 t3 low (0) table 2. default phases for horizontal signal edges
cs7620 ds301pp2 19 3.4.5 vertical timing generator the signals involved in the vertical timing genera- tor are the vertical shift clocks v1 through v4 and the storage clocks s1 through s4. the vertical tim- ing generator generates the signals needed by the ccd to shift charge vertically down into the hori- zontal shift register. the chip is the timing master, and it generates the signals needed by the horizon- tal timing generator and other modules to operate. the timing generator is controlled externally by various signals; the falling edge of the input signal expose sets the part into readout mode, and after this edge, it generates the timing signals to output a full frame, provided that rst and pwr_dn are not active. the mode register selects the ccd timing, and the resolution mode to be generated. please refer to ibm-ccd datasheet for more info. the timing module's functionality can be config- ured through the use of registers. note that before entering a preview mode, all of the programmable parameters must be set prior to this. shiftl_num is the number of lines in the shift buff- er. tdv is the length of the minimum vertical timing interval measured in pixel clocks. num_pixels is the number of pixels per line num_lines is the number of lines per frame. v_polarity allows to switch the polarity of all the vertical timing signals going to the ccd. blk_begin is the first black pixel in a line blk_end is the last black pixel in a line drk_rws_fst is the number of black lines to be readout at the beginning of the frame drk_rws_lst is the number of black lines to be readout at the end of the frame 3.4.6 frame timing figures 21 and 22 illustrates the frame timing for the low and high resolution modes. hsync is high during the active pixel area, and it is low during vertical shift (horizontal and vertical blanking periods). rd_out is triggered by the falling edge of ex- pose, it is delayed by the chip latency, and it switches back high once the last pixel has been read out of the cs7620. rd_out is low during the ac- tive pixel areas and during the horizontal blanking periods (vertical line shifts) and it goes high during the vertical blanking period, between frames. the dotted lines in figures 21 and 22 correspond to the vsync option which can be enabled by writing a one to register vsync_md (register 25h bit 5). this causes the rd_out signal to behave like a vertical sync signal. it makes the signals hsync and rd_out the same length at the beginning of a new frame (see figures 21 and 22). 3.5 frequency synthesizer since multiple clock phases and timing are re- quired for the pixel rate clocks controlling the ccd imager, the clock generator contains a pll circuit to generate the proper timing. frequency synthe- sizer parameters on page 6 shows the require- ments for this pll. the frequency of the input clock may be set from 1 to 20x the pixel clk fre- quency, in integer multiples. the frequency used is mode value mode 000 ibm35ccd2pix1 and ibm35ccdpix13 ccd high resolution mode 001 ibm35ccd2pix1 ccd low resolution (viewfinder) mode 010-100 reserved 101 ibm35ccd13pix ccd (2x2) low resolu- tion (viewfinder) mode 110 ibm35ccd13pix ccd (3x4) low resolu- tion (viewfinder) mode 111 external timing used table 3. different resolution operating modes
cs7620 20 ds301pp2 register programmable in terms of multiples of the pixel clock rate. 3.6 8-bit general purpose dacs two 8-bit current-output dacs are available for external use. table 4 shows the output specifica- tions of these dacs. 3.7 stand by mode stand-by mode can be entered using the pwr_dn pin. all circuitry on chip including the dacs can be powered down. various functional blocks can be powered down individually, and are controlled through registers. note that the dacs can be pow- ered down in that way if not in use. during stand by mode, the register contents are maintained and expose rd_out hsync v1 ... v4 h1 ... h4 s1 ... s4 vsync_md = 1 vsync_md = 0 262 lines first read-out line last read-out line figure 21. high resolution mode expose rd_out hsync v1 ... v4 h1 ... h4 s1 ... s4 vsync_md = 1 vsync_md = 0 262 lines first read-out line last read-out line dont care 262 lines first read-out line picture n picture n picture (n+1) figure 22. low resolution mode parameter high impedance mode low impedance mode iout 2.155 ma 8.7 ma loading 464 w 115 w table 4. general purpose dac specifications
cs7620 ds301pp2 21 do not have to be reprogrammed at the next power up. 3.8 preview mode it is strongly recommend that the chip should be kept in stand by mode when not in use in order to save power. when in preview mode, a user may wish to cut down the resolution of the adc output to 6 bits in order to reduce the power consumption of the cs7620. in this mode, the current is reduced by 20 ma. with the drx (dynamic range exten- sion) circuitry, 3 bits of dynamic range are added to the 6-bit adc output producing a 9-bit output. the pins dout[12:4] are used to output the digitized data in preview or stand by mode. 3.9 serial interface the serial interface is designed to allow high speed input to control the chips registers. the specifica- tions on this interface are as follows: asserting the enable pin, sen , enables the serial interface to perform data transfers. data present on the sdati pin is latched into the cs7620 on each rising edge of the serial clock, sclk. data output on sdato from the cs7620 is clocked out on the rising edge of sclk. the cs7620 receives only the first 16 rising edges of the sclk while sen is low and then ignores any remaining sclk and sdati information. if sen goes high before 16 sclk pulses have been received, the cs7620 aborts the serial transfer. the first bit is the r/w bit. r/w = 1 identifies the transfer as a read. if (0), the transfer is a write. the next seven bits define the address. for write trans- fers, the second byte of the 16-bit packet contains the data byte. for read transfers, the cs7620 out- puts the read data on sdato after accepting the address. address and data are transferred msb first. when not reading out data, the sdato pin is not driven by the chip (hi-z state). the timing diagrams and specifications are shown in serial interface timing specifications on page 7 and figures sen timing, read data timing, and serial write timing on page 7. 3.10 recommended register settings these are the values that need to be written to the registers to change the configuration of the cs7620 to work with each ccd in either low resolution or high resolution mode. (2 2) refers to a rgrgrg pattern and (3 4) refers to a rgbrgb pattern ccd.
cs7620 22 ds301pp2 2.0m pixel (default) high resolution 2.0m pixel (2x2) low resolution 2.0m pixel (3x4) low resolution tim_modes(06h) 000b 001b 001b num_lines[12:8](17h) 05h 05h 05h num_lines[7:0](18h) 1ch 1ch 1ch num_pixels[12:8](19h) 06h 06h 06h num_pixels[7:0](1ah) 93h 93h 93h drk_rws (frst/lst)(1bh) a4h 20h 20h blk_begin(1ch) 04h 04h 04h blk_end(1dh) 3fh 3fh 3fh act_rws (frst/lst)(1eh) b6h 32h 32h act_begin(1fh) 4bh 4bh 4bh tdv(20h) 01h 01h 01h shiftl_num[8](21h) 01h 01h 01h shiftl_num[7:0](22h) 06h 06h 06h lowres_sen[3:0](25h) xxxxb 0000b 0100b 2x sens 0001b 2x sens 0101b 3x sens 0000b 0010b 2x sens table 5. ibm35ccd2pix1 1.3m pixel high resolution 1.3m pixel (2x2) low resolution 1.3m pixel (3x4) low resolution tim_modes(06h) 000b 101b 110b num_lines[12:8](17h) 04h 04h 04h num_lines[7:0](18h) 1ch 1ch 1ch num_pixels[12:8](19h) 05h 05h 05h num_pixels[7:0](1ah) 50h 50h 50h drk_rws (frst/lst)(1bh) a4h 20h 20h blk_begin(1ch) 04h 04h 04h blk_end(1dh) 3fh 3fh 3fh act_rws (frst/lst)(1eh) b6h 42h 42h act_begin(1fh) 4bh 4bh 4bh tdv(20h) 01h 01h 01h shiftl_num[8](21h) 01h 01h 01h shiftl_num[7:0](22h) 06h 06h 06h lowres_sen[3:0](25h) xxxxb 0000b 0100b 2x sens 0000b 0010b 2x sens table 6. ibm35ccd13pix
cs7620 ds301pp2 23 60.4 k w 10 k w 464 w 60.4 k w 10 k w 464 w substrate voltage to ccd to ccd 10 k w 1% 1 f vertical drivers to microcontroller to ccd to ccd 1000 pf 100 k w vcc vaa clk_in reset from microcontroller from ccd nc nc xtal_in bypass_pll rst diag0 diag1 scan_mode test line_ena clamp 5 11253240 43 39 38 29 30 17 16 3 2 13 dout[0:12] clko hsync rd_out v[1:4] s[1:4] h[1:4] rg ref_capp ref_capn 4 4 4 52 12 13 37 28 27 21 15 14 6 7 8 9 23 4 10243141 19 18 power_down expose sclk sdati sdato sen ain bg_res dac_out1 dac_out2 gnd cs7620 figure 23. typical connection diagram using vertical and horizontal timing mode
cs7620 24 ds301pp2 60.4 k w 10 k w 464 w 60.4 k w 10 k w 464 w substrate voltage to ccd to ccd 10 k w 1% 1 f to microcontroller to ccd 1000 pf 100 k w vcc vaa clk_in reset from microcontroller from ccd nc nc xtal_in bypass_pll rst diag0 diag1 scan_mode test line_ena clamp 5 11253240 43 39 38 29 30 17 16 3 2 13 dout[0:12] clko hsync rd_out v[1:4] s[1:4] h[1:4] rg ref_capp ref_capn 4 4 4 52 12 13 37 28 27 21 15 14 6 7 8 9 23 4 10243141 19 18 power_down expose sclk sdati sdato sen ain bg_res dac_out1 dac_out2 gnd cs7620 nc nc nc figure 24. typical connection diagram using horizontal only timing mode
cs7620 ds301pp2 25 60.4 k w 10 k w 464 w 60.4 k w 10 k w 464 w substrate voltage to ccd 10 k w 1% 1 f to microcontroller vcc vaa reset from microcontroller from ccd nc nc xtal_in bypass_pll rst diag0 diag1 scan_mode test line_ena clamp 5 11253240 43 39 38 29 30 17 16 3 2 13 dout[0:12] clko hsync rd_out v[1:4] s[1:4] h[1:4] rg ref_capp ref_capn 4 4 4 52 12 13 37 28 27 21 15 14 6 7 8 9 23 4 10243141 19 18 power_down expose sclk sdati sdato sen ain bg_res dac_out1 dac_out2 gnd cs7620 nc nc nc sampling signals vdd nc nc to rg bias circuitry ck_ft ck_dt figure 25. typical connection diagram using slave mode
cs7620 26 ds301pp2 4 register descriptions register (hex) register function access default value (hex) 00h software reset w 00 01h power down control 1 r/w 00h 02h power down control 2 r/w 00 03h-05h reserved 06h operation control 1 r/w 09h 07h operation control 2 r/w 04h 08h-0ch reserved 0dh black level control - accumulator (lsb) r/w 00h 0eh black level control - accumulator (msb) r/w 01h 0fh black level control - loop gain, clamp length r/w 0ah 10h gain calibration - offset 1 r/w 00h 11h gain calibration - offset 2 r/w 00h 12h gain calibration - offset 3 r/w 00h 13h-15h reserved 16h gain calibration - fixed gains r/w 00h 17h timing control - number of lines (msbs) r/w 05h 18h timing control - number of lines (lsbs) r/w 1ch 19h timing control - number of columns (msbs) r/w 06h 1ah timing control - number of columns (lsbs) r/w 93h 1bh timing control - number of dark rows r/w a4h 1ch timing control - start of black pixels r/w 04h 1dh timing control - end of black pixels r/w 3fh 1eh timing control - number of rows until active r/w c6h 1fh timing control - start of active pixels r/w 4bh 20h timing control - vertical time division r/w 01h 21h timing control - lines in storage buffer (msb) r/w 01h 22h timing control - lines in storage buffer (lsbs) r/w 06h 23h timing control - extra lines of exposure in low resolution mode (msbs) r/w 00h 24h timing control - extra lines of exposure in low resolution mode (lsbs) r/w 00h 25h timing control - vsync mode, low res sensitivity, lines of exposure in low res mode (msb) r/w 01h 26h timing control - lines of exposure in low res mode (lsb) r/w 06h 27h reserved 28h timing control - polarity of vertical shift outputs r/w ffh 29h horizontal timing control - h1 r/w 68h 2ah horizontal timing control - h2 r/w 7ah 2bh horizontal timing control - h3 r/w 4ch 2ch horizontal timing control - h4 r/w 1eh 2dh horizontal timing control - analog delays r/w 00h 2eh compander - black slope, slopes (msbs) r/w 00h 2fh compander - slope1 (lsbs) r/w a8h 30h compande - slope2 (lsbs) r/w 60h 31h compander - slope3 (lsbs) r/w 20h table 7. register description
cs7620 ds301pp2 27 32h compander - slope4 (lsbs) r/w 07h 33h compander - offset1 r/w 08h 34h compander - offsets (msbs) r/w 0bh 35h compander - offset2 (lsbs) r/w bfh 36h compander - offset3 (lsbs) r/w 05h 37h compander - offset4 (lsbs) r/w 20h 38h compander - x1 (msbs) r/w 03h 39h compander - x1 (lsbs) r/w 20h 3ah compander - x2 (msbs) r/w 05h 3bh compander - x2 (lsbs) r/w 18h 3ch compander - x3 (msbs) r/w 0bh 3dh compander - x3 (lsbs) r/w 58h 3eh power_up counter r/w 7dh 3fh valid_data/dout edge/clock_in divider r/w 01h 40h dac #1 control r/w 00h 41h dac #2 control r/w 00h 42h-7dh reserved 7eh device id r ech 7fh rev code r 02h register (hex) register function access default value (hex) table 7. register description (continued)
cs7620 28 ds301pp2 4.1 reset default = 00; write (address 00h) 4.2 power down control 1 default = 00h; read/write (address 01h) bit number 76543210 bit name reserved sft_rst default -------00 bit mnemonic function 7:1 - reserved 0sft_rst software reset: when this bit is written with a 1, all of the digital circuitry and the registers will reset to their default values. it automatically clears after 4 pixel clock periods. the clocks remain running during the reset period. bit number 76543210 bit name pd_vga pd_adc pd_ref reserved pd_dac1 pd_dac2 reserved default 000 - - 00 - bit mnemonic function 7 pd_vga drx front end power down: when written with a 1, the drx front end circuitry powers down. used for test purposes only. 6 pd_adc adc power down: when written with a 1, the analog-to-digital converter circuitry powers down. used for test purposes only. 5pd_ref voltage reference power down: when written with a 1, the voltage refer- ence generator powers down. used for test purposes only. 4:3 - reserved 2 pd_dac1 dac #1 power down: when written with a 1, dac #1 powers down. should be powered down when dac#1 is not being used by the system. 1 pd_dac2 dac #2 power down: when written with a 1, dac #2 powers down. should be powered down when dac#2 is not being used by the system. 0- reserved
cs7620 ds301pp2 29 4.3 power down control 2 default = 00; read/write (address 02h) 4.4 operation control 1 default = 09h; read/write (address 06h). bit number 76543210 bit name reserved pd_htim reserved default ------0- bit mnemonic function 7:2 - reserved 1 pd_htim horizontal timing power down: when written with a 1, the horizontal tim- ing generator powers down. should be powered down when horizontal timing is not being used by the system. in this mode the chip is a timing slave. 0- reserved bit number 76 5 4 3210 bit name low_res tim_modes2 tim_modes1 tim_modes0 bits_out1 bits_out1 blk_dis off_range default 00 0 0 1001 bit mnemonic function 7 low_res low resolution mode: this mode can be used to cut the current consump- tion of the chip by 20 ma. the output of the adc will have 6 bits of resolution in this mode, and the output of the chip will have 9 bits after using the drx circuitry. it is intended to be used when driving an lcd display or any other time when a lower resolution picture is acceptable. 6 tim_modes2 timing generator select: the type of timing signals output by the chip can be selected using these control bits. ibm35ccdpix13 2x2 and ibm35ccdpix13 3x4 modes, support type ibm ccds with different color filter patterns. note that register 1bh needs to be rewritten with correct low resolu- tion values for black rows if low resolution mode is used (see table 3). the chips default power up setting is hardcoded to be ibm35ccd2pix1. so that the registers that hold the number of lines, the number of pixels per line, the number of black lines, and the number of active lines are all set up to their proper values. if ibm35ccdpix13 is to be used, the values on all those reg- isters has to be changed appropriately (see tables 5 and 6). 5 tim_modes1 4 tim_modes0
cs7620 30 ds301pp2 3 bits_out1 number of data bits out: the range of the output data can be determined by these bits. the data internal to the chip has a 13-bit range. the output can be this full range, half this range (12 bits), or an eighth of this range (10 bits). if 12-bit data is selected, the top half of the 13-bit range is saturated to the maximum 12-bit code. if 10-bit data is selected, the compander curve which is user programmable is employed to map the 13-bit data to the 10-bit output. 0 - 10 bits output 1 - 10 bits output 2 - 13 bits output 3 - 12 bits output 2 bits_out1 1 blk_dis black level loop disabled: if the user chooses to adjust the black level him- self through register access, he may disable the internal black level loop. this loop usually updates the black level to what it calculates to be the correct level. if disabled, the offset used will be determined from the value written in the black level accumulator register. 0 - internal black level loop is enabled 1 - black level loop is disabled 0 off_range offset range: the black level loop is used to cancel any offsets from the ccd and chip circuitry. if the offsets are small, the user has the option to de- crease the offset cancellation range for the added advantage of increasing the resolution of the offset cancellation. 0 - smaller offset cancellation range used (~50 mv) 1 - larger offset cancellation range used (~100 mv) mode value mode 000 ibm35ccd2pix1 and ibm35ccdpix13 ccd high resolution mode 001 ibm35ccd2pix1 ccd low resolution (viewfinder) mode 010 reserved 100 reserved 101 ibm35ccd13pix ccd (2x2) low resolution (viewfinder) mode 110 ibm35ccd13pix ccd (3x4) low resolution (viewfinder) mode 111 external timing used table 8. different resolution operating modes bit mnemonic function
cs7620 ds301pp2 31 4.5 operation control 2 default = 04h; read/write (address 07h). bit number 76543210 bit name pol_hsyncb pol_rd_outb dac2_mode dac1_mode fs_lvl1 fs_lvl0 gain_cal1 gain_cal2 default 0 0 0 0 0 1 0 0 bit mnemonic function 7 pol_hsyncb hsync polarity: the hsync signal output from the chip defaults to be high when data is being shifted out of the ccd and low during all other times (the vertical shift time of each line and idle times). this polarity may be swapped with this bit so that hsync is low when data is being shifted out and high all other times. 0 - hsync is high during horizontal data read out 1 - hsync is low during horizontal data read out 6 pol_rd_outb rd_out polarity: the rd_out signal output from the chip defaults to be low when the ccd data readout is being performed and high when not reading out data from the ccd. the polarity of this signal may be swapped with this bit so that rd_out is high during readout and low when not reading data out. note that when this bit is redefined in order to function as a vertical sync signal, this bit will serve to swap its polarity as well. 5 dac2_mode dac #2 current mode: there are two modes for the output current of dac2. default mode provides a current range of 2.2 ma for the 8-bit input word. this will increment the current by ~8.6 a per lsb code change. the high current mode can be selected using this bit to change the current range to 8.7 ma for the 8-bit input word. this will increment the current by ~34 a per lsb code change. 4 dac1_mode dac #1 current mode: there are two modes for the output current of dac1. default mode provides a current range of 2.2 ma for the 8-bit input word. this will increment the current by ~8.6 a per lsb code change. the high current mode can be selected using this bit to change the current range to 8.7 ma for the 8-bit input word. this will increment the current by ~34 a per lsb code change. 3 fs_lvl1 full scale level: this is used to set the full scale input range of the cs7620. since ccds have various saturation levels, it is advantageous to set the full scale input range of the cs7620 to match the saturation level of the ccd used. table 9 shows the full scale level choices 2 fs_lvl0 1 gain_cal1 gain calibration #1: a calibration of the gain stages is required to insure a monotonic digital output. in default (0), this calibration is automatically done after a chip reset and after coming up from power down mode. if the recalibra- tion after power down is not desired, this bit can be written with a 1 to force a calibration only after a chip reset. 0 gain_cal2 gain calibration #2: a calibration of the gain stages is required to insure a monotonic digital output. this calibration is transparent to the user. however, if the user wishes to force a calibration to occur, he may do so by setting this bit to 1, which will invoke a gain calibration sequence immediately. this bit automatically clears itself after a calibration has been initiated.
cs7620 32 ds301pp2 4.6 black level control - accumulator (lsb) default = 00h; read/write (address 0dh) 4.7 black level control - accumulator (msb) default = 01h; read/write (address 0eh). fs_lvl full scale voltage 00 0.53 v 01 1.07 v 1x 1.60 v table 9. full scale level choices bit number 76543210 bit name accumulator7 accumulator6 accumulator5 accumulator4 accumulator3 accumulator2 accumulator1 accumulator0 default 00000000 bit mnemonic function 7 accumulator7 black level accumulator: see description of register 0eh. 6 accumulator6 5 accumulator5 4 accumulator4 3 accumulator3 2 accumulator2 1 accumulator1 0 accumulator0 bit number 76543210 bit name reserved accumulator8 default ------- 1 bit mnemonic function 7:1 - reserved 0 accumulator8 black level accumulator: the black level accumulator is a 9 bit number rep- resenting an amount of offset added to the input of the cds circuit. the black level loop alters the black level accumulator value to make the output of the adc settle to code 64 during black pixels. if desired the black loop may be disabled and written to manually to add any desired amount of offset. there is a total of ~100 mv of offset range if the offset range register setting is set to 1 or ~50 mv when this register setting is set to 0. this offset range is used to correct for ccd offsets plus internal offsets generated in the analog path of this chip. the offset range before subtracting the internal offsets is as shown in table 10 below with the worst case internal offsets being 17 mv. offset range (reg 06h bit 0) max offset blk acc=511 min offset blk acc=0 accumulator lsb size 1 ~30 mv ~-72 mv ~0.2 mv 0 ~11 mv ~-40 mv ~0.1 mv table 10. offset range
cs7620 ds301pp2 33 4.8 general black level the black loop is a feedback system that causes the adc output to settle to 64 during the register defined black pixels. this has the purpose of removing any ccd and system offsets and defining 64 as the known black level. the loop has an exponential settling response and the time constant of this loop is effected by the black loop gain and the number of black pixels to accumulate before updating the black accumulator. see figure 10 for a block diagram of the black level. 4.9 black level control - loop gain, clamp length default = 0ah; read/write (address 0fh). where: k = 1/256*blk_gain n = black loop clamp length = blk_clp_l[5:0] fu = update rate bit number 76543210 bit name blk_gain1 blk_gain0 blk_clp_15 blk_clp_14 blk_clp_13 blk_clp_12 blk_clp_11 blk_clp_10 default 00001010 bit mnemonic function 7 blk_gain1 black loop gain factor: the black loop gain factor can be set to 1x,2x,4x,or 8x and is simply a multiplying constant to effect the weight of each black pixel before it is accumulated. 00 - defines a gain of 1x 01 - defines a gain of 2x 10 - defines a gain of 4x 11 - defines a gain of 8x 6 blk_gain0 5 blk_clp_15 black loop clamp length: the black clamp length effects the loop time con- stant and also acts to average out noise in the black level. the larger this val- ue the more pixels that are summed before the loop is updated which causes greater averaging and a smaller settling time constant. table 11 shows the black loop time constant for various settings of offset range (register 06h, bit 0) and fixed gain settings (register 16h, bits 5-3). 4 blk_clp_14 3 blk_clp_13 2 blk_clp_12 1 blk_clp_11 0 blk_clp_10 fixed gain (register 16h) offset range = 1 offset range = 0 not fixed -1/(ln(1-nk))(1/fu) -1/(ln(1-nk/2))(1/fu) x1 -1/(ln(1-nk/8))(1/fu) -1/(ln(1-nk/16))(1/fu) x2 -1/(ln(1-nk/4))(1/fu) -1/(ln(1-nk/8))(1/fu) x4 -1/(ln(1-nk/2))(1/fu) -1/(ln(1-nk/4))(1/fu) x8 -1/(ln(1-nk))(1/fu) -1/(ln(1-nk/2))(1/fu) table 11. black loop time constant
cs7620 34 ds301pp2 4.10 gain calibration - offset 1 default = 00h; read/write (address 10h) 4.11 gain calibration - offset 2 default = 00h; read/write (address 11h) bit number 76543210 bit name gain_offset17 gain_offset16 gain_offset15 gain_offset14 gain_offset13 gain_offset 12 gain_offset11 gain_offset10 default 00000000 bit mnemonic function 7 gain_offset17 gain calibration offset 1: offset added to 4x gain segment, values are in 2s complement. see details in register 12h. 6 gain_offset16 5 gain_offset15 4 gain_offset14 3 gain_offset13 2 gain_offset12 1 gain_offset11 0 gain_offset10 bit number 76543210 bit name gain_offset27 gain_offset26 gain_offset25 gain_offset24 gain_offset23 gain_offset 22 gain_offset21 gain_offset20 default 00000000 bit mnemonic function 7 gain_offset27 gain calibration offset 2: offset added to 2x gain segment, values are in 2s complement. see details in register 12h. 6 gain_offset26 5 gain_offset25 4 gain_offset24 3 gain_offset23 2 gain_offset22 1 gain_offset21 0 gain_offset20
cs7620 ds301pp2 35 4.12 gain calibration - offset 3 default = 00h; read/write (address 11h) gain calibration - fix gains default = 00h; read/write (address 16h) bit number 76543210 bit name gain_offset 37 gain_offset 36 gain_offset 35 gain_offset 34 gain_offset 33 gain_offset 32 gain_offset 31 gain_offset 30 default 00000000 bit mnemonic function 7 gain_offset37 gain calibration offset 3: offset added to 1x gain segment. values are in 2s complement. these registers are used to report some of the calibration settings. after cal- ibration is performed the gain offset registers are automatically updated with values needed for the drx circuitry to operate correctly. these registers should not be written to since this will remove the proper settings found during calibration. the gain offset values are used to add an offset to the output of the adc when using different analog gain settings (see equations below). the purpose of this is to produce a continuous transition between the different gain settings so that the final 13 bit output is monotonic and has no undesired artifacts. (see figure 26) {adc_outif in the 8x gain segment} dout[12:0] ={adc_out*2+offset1if in the 4x gain segment} {adc_out*4+offset2*2if in the 2x gain segment} {adc_out*8+offset3*4if in the 1x gain segment} 6 gain_offset36 5 gain_offset35 4 gain_offset34 3 gain_offset33 2 gain_offset32 1 gain_offset31 0 gain_offset30 bit number 76543210 bit name reserved fixed_gain2 fixed_gain1 fixed_gain0 reserved default -- 000 --- bit mnemonic function 7:6 - reserved 5 fixed_gain2 fixed gain: this is used to turn off the drx functionality and apply a fixed gain to the input before reaching the adc. a setting of 000 is used for normal operation this will yield the largest dynamic range by switching the front end gain relative to the amplitude of the input signal. the settings 001, 010, 011, and 100 are for fixed gains of 1x, 2x, 4x, and 8x respectively. figure 27 shows the transfer function of the output of the adc for a given input with the various fixed gain settings. 4 fixed_gain1 3 fixed_gain0 2:0 - reserved
cs7620 36 ds301pp2 4.13 timing control - number of lines (msbs) default = 05h; read/write (address 17h) bit number 76543210 bit name reserved num_lines12 num_lines11 num_lines10 num_lines9 num_lines8 default -- - 00101 bit mnemonic function 7:5 - reserved 4 num_lines12 line numbers: bits 12 through 8 of the number of lines. (see figure 26) 3 num_lines11 2 num_lines10 1 num_lines9 0 num_lines8 1024 512 1x 2x 4x 8x adc out input 1.07 8192 4096 1024 2048 64 figure 26. transfer function of analog input to digital output (assuming full scale level of 1.07v) 64 input use offset1 use offset2 use offset3
cs7620 ds301pp2 37 1024 1x 2x 4x 8x adc output 1024 figure 27. transfer function of adc with fixed gain settings (assuming full scale level of 1.07v) input 0.13 0.27 0.53 1.07 adc output 1x input (v) 1.07 1024 adc output 2x input (v) 1.07 0.53 1024 adc output 4x input (v) 1.07 1024 adc output 8x input (v) 1.07 0.53 0.27 0.53 0.13 0.27 fixed gain = 001 fixed gain = 000 fixed gain = 011 fixed gain = 100 fixed gain = 010
cs7620 38 ds301pp2 4.14 timing control - number of lines (lsbs) default = 1ch; read/write (address 18h) 4.15 timing control - number of columns (msbs) default = 06h; read/write (address 19h) bit number 76543210 bit name num_lines7 num_lines6 num_lines5 num_lines4 num_lines3 num_lines2 num_lines1 num_lines0 default 0 0 0 11100 bit mnemonic function 7 num_lines7 line numbers: bits 7 through 0 of the number of lines. the number of lines registers should be written with the total number of lines (rows) of the ccd including any black lines (this should not include the trans- fer area). the default value is 1308 which is the number of lines in a ibm35ccd2pix1 ccd. (see figure 28) 6 num_lines6 5 num_lines5 4 num_lines4 3 num_lines3 2 num_lines2 1 num_lines1 0 num_lines0 bit number 76543210 bit name reserved num_pixels12 num_pixels11 num_pixels10 num_pixels9 num_pixels8 default - - - 00110 bit mnemonic function 7:5 - reserved 4 num_pixles12 column numbers: bits 12 through 8 of the number of columns. (see figure 28) 3 num_pixels11 2 num_pixels10 1 num_pixels9 0 num_pixels8
cs7620 ds301pp2 39 4.16 timing control - number of columns (lsbs) default = 93h; read/write (address 1ah) 4.17 timing control - number of dark rows default = a4h; read/write (address 1bh) bit number 76543210 bit name num_pixels7 num_pixels6 num_pixels5 num_pixels4 num_pixels3 num_pixels2 num_pixels1 num_pixels0 default 10010011 bit mnemonic function 7 num_pixels7 column numbers: bits 7 through 0 of the number of columns. the number of columns registers should be written with the total number of pixels per line (columns) of the ccd including any black pixels and any extra pixels. (due to ccd horizontal register latency) the default value (num_pixels[12:0]) is 1683 which is the number of rows in a ibm35ccd2pix1 ccd. (see figure 28) 6 num_pixels6 5 num_pixels5 4 num_pixels4 3 num_pixels3 2 num_pixels2 1 num_pixels1 0 num_pixels0 bit number 76543210 bit name drk_rws_frst3 drk_rws_frst2 drk_rws_frst1 drk_rws_frst0 drk_rws_lst3 drk_rws_lst2 drk_rws_lst1 drk_rws_lst0 default 10100100 bit mnemonic function 7 drk_rws_frst3 dark rows: the dark rows registers should be written with the number of rows at the top and bottom of the ccd. please note that drk_rws_frst refers to the first rows to be read out. these are the rows at the top of the image, which get inverted through the lens, and get focused onto the bottom rows of the ccd. the cs7620 uses these rows to acquire the proper black level. the default value is 10 and the correct value to work with the ibm35ccd2pix1 ccd. (see figure 28) 6 drk_rws_frst2 5 drk_rws_frst1 4 drk_rws_frst0 3 drk_rws_lst3 dark rows: the dark rows registers should be written with the number of rows at the top and bottom of the ccd. note that drk_rws_lst refers to the last rows to be read out. this are the rows at the bottom of the image, which get inverted through the lens, and get fo- cused onto the top rows of the ccd. the cs7620 uses these rows to acquire the proper black level. the default value is 4 and is the correct value to work with the ibm35ccd2pix1 ccd. (see figure 28) 2 drk_rws_lst2 1 drk_rws_lst1 0 drk_rws_lst0
cs7620 40 ds301pp2 4.18 timing control - start of black pixels default = 04h; read/write (address 1ch) 4.19 timing control - end of black pixels default = 3fh; read/write (address 1dh) bit number 76543210 bit name reserved blk_begin3 blk_begin2 blk_begin1 blk_begin0 default ---- 0100 bit mnemonic function 7:4 - reserved 3 blk_begin3 black pixels: this register indicates the beginning of the black pixels within a horizontal line. before the black pixels, there can be some extra pixels, due to latency through the horizontal shift register inside the ccd. the default value for this register is 4, since ibm35ccd2pix1 has 3 extra pixels. (see figure 28) 2 blk_begin2 1 blk_begin1 0 blk_begin0 bit number 76543210 bit name reserved blk_end6 blk_end5 blk_end4 blk_end3 blk_end2 blk_end1 blk_end0 default - 0111111 bit mnemonic function 7- reserved 6 blk_end6 black pixels: this register indicates the end of the black pixels within the hor- izontal line. this register is used by the black level loop together with blk_begin, to acquire the proper black level on a line by line basis. since the loop has some latency, the value stored in this register, should be 10 less than the actual last black pixel in each line. since in ibm35ccd2pix1, this number is 73, the default is set to 63. (see figure 28) 5 blk_end5 4 blk_end4 3 blk_end3 2 blk_end2 1 blk_end1 0 blk_end0
cs7620 ds301pp2 41 4.20 timing control - number of rows until active default = c6h; read/write (address 1eh) bit number 76543210 bit name act_rws_frst3 act_rws_frst2 act_rws_frst1 act_rws_frst0 act_rws_lst3 act_rws_lst2 act_rws_lst1 act_rws_lst0 default 11000110 bit mnemonic function 7act_rws_frst3 active rows: act_rws_frst corresponds to the first group of non active rows at the top of the image, which get inverted through the lens, and get focused onto the bottom rows of the ccd. the register value is used by the cs7620 when the part is in the valid data mode to generate the data valid signal on the clko pin. valid data can be set through the above mentioned registers together with act_begin(1fh) to define a subset of pixels to be passed to the subsequent asic or dsp component. this subset may or may not include dark rows and/or dark pixels. please refer to figure 28. 6act_rws_frst2 5act_rws_frst1 4act_rws_frst0 3 act_rws_lst3 active rows: act_rws_lst corresponds to the last group of non active rows at the bottom of the image, which get inverted through the lens, and get focused onto the top rows of the ccd. the register value is used by the cs7620 when the part is in the valid data mode to generate the data valid signal on the clko pin. valid data can be set through the above mentioned registers together with act_begin(1fh) to define a subset of pixels to be passed to the subsequent asic or dsp component. this subset may or may not include dark rows and/or dark pixels. please refer to figure 28. 2 act_rws_lst2 1 act_rws_lst1 0 act_rws_lst0 dark pixels drk_rws_lst (1bh) blk_begin (1ch) blk_end (1dh) dark pixels act_rws_lst (1eh) num_pixels (19h, 1ah) num_lines (17h, 18h) act_rws_frst (1eh) shiftl_num (21h, 22h) drk_rws_frst (1bh) active pixels transfer area figure 28. typical ccd pixel arrangement
cs7620 42 ds301pp2 4.21 timing control - start of active pixels default = 4bh; read/write (address 1fh) 4.22 timing control - vertical time division default = 01h; read/write (address 20h) bit number 76543210 bit name act_begin7 act_begin6 act_begin5 act_begin4 act_begin3 act_begin2 act_begin1 act_begin0 default 01001011 bit mnemonic function 7 act_begin7 active pixels: this register should be programmed with the pixel number of the first active pixel to be read out. that is the first pixel after the extra pixels, the black pixels, and the grey pixel. this register value is used by the cs7620 when the part is in the valid data mode to generate the data valid signal on the clko pin. valid data can be set through the above mentioned registers together with act_begin(1fh) to define a subset of pixels to be passed to the subsequent asic or dsp component. this subset may or may not include dark rows and/or dark pixels. please refer to figure 28. the default value is set to 75, which is the sum of the blk_end register (1dh) and act_rws_lst register (1eh). 6 act_begin6 5 act_begin5 4 act_begin4 3 act_begin3 2 act_begin2 1 act_begin1 0 act_begin0 bit number 76543210 bit name reserved tdv4 tdv3 tdv2 tdv1 tdv0 default --- 00001 bit mnemonic function 7:5 - reserved 4tdv4 critical timing: this determines the width of the minimum vertical division measured in pixel clocks. (one vertical pixel shift (row) requires 8 vertical time division slots) see figure 33. 3tdv3 2tdv2 1tdv1 0tdv0
cs7620 ds301pp2 43 4.23 timing control - lines in storage buffer (msbs) default = 01h; read/write (address 21h) 4.24 timing control - lines in storage buffer (lsbs) default = 06h; read/write (address 22h) 4.25 timing control - extra lines of exposure in low resolution mode (msbs) default = 00h; read/write (address 23h) bit number 76543210 bit name reserved shiftl_num9 shiftl_num8 default ------ 01 bit mnemonic function 7:2 - reserved 1 shiftl_num9 storage buffer lines: this value must be programmed for proper operation in both high and low resolution modes. please refer to figure 28. 0 shiftl_num8 bit number 76543210 bit name shiftl_num7 shiftl_num6 shiftl_num5 shiftl_num4 shiftl_num3 shiftl_num2 shiftl_num1 shiftl_num0 default 00000110 bit mnemonic function 7 shiftl_num7 storage buffer lines: this value must be programmed for proper operation in both high and low resolution modes. the default value for shiftl_num is 262. please refer to figure 28. 6 shiftl_num6 5 shiftl_num5 4 shiftl_num4 3 shiftl_num3 2 shiftl_num2 1 shiftl_num1 0 shiftl_num0 bit number 76543210 bit name reserved n_extra10 n_extra9 n_extra8 default ----- 000 bit mnemonic function 7:3 - reserved 2 n_extra10 extra lines: see description for register 24h below. 1 n_extra9 0 n_extra8
cs7620 44 ds301pp2 4.26 timing control - extra lines of exposure in low resolution mode (lsbs) default = 00h; read/write (address 24h) 4.27 timing control - vsync mode, lines of exposure in low resolution mode (msbs) default = 01h; read/write (address 25h) bit number 76543210 bit name n_extra7 n_extra6 n_extra5 n_extra4 n_extra3 n_extra2 n_extra1 n_extra0 default 00000000 bit mnemonic function 7 n_extra7 extra lines: this allows for increased exposure time while in low resolution mode. in low resolution mode, the cs7620 continuously outputs data on a frame by frame basis; so it can drive a lcd panel in a video mode. in this mode the cs7620 ignores the expose signal. the default expose time is equivalent to 262 line times (see registers 25h and 26h, n_int). n_extra provides a way to increase the exposure time beyond the one which is set by register n_int (25h and 26h). the value of n_extra corresponds to the number of line times. 6 n_extra6 5 n_extra5 4 n_extra4 3 n_extra3 2 n_extra2 1 n_extra1 0 n_extra0 bit number 76543210 bit name reserved vsync_md lowres_sen3 lowres_sen2 lowres_sen1 lowres_sen0 n_int8 default -- 000001 bit mnemonic function 7:6 - reserved 5 vsync_md vertical sync: vsync_md, will switch the rd_out pin to output a vertical sync signal on this pin when the vsync_md register is set to 1. the default is 0 which outputs the rd_out signal (see figures 21 and 22).
cs7620 ds301pp2 45 4 lowres_sen3 sensitivity in low resolution mode: lowres_sens provides a way to increase the sensitivity during low resolution mode (see figure 33). for proper settings of these values, please refer to the ccd data sheets. in order to allow for a video mode, (low resolution) ibm 1.3mpixel and 2.0mpixel have a storage area that is in both cases 262 lines long. the use of this transfer area, is to keep the pixels cov- ered from light during readout. this must be done because it is not practical to have a shutter at such high speed. without the storage area the picture would be smeared, since the last line to be readout would have had a lot more exposure time than the first one. to solve this the storage area is used in the following manner. in the 1.3mpixel there are 4 times more active lines than there are storage lines. the low resolution mode consists of two steps: step 1: transfer: during this step, the active lines are subsampled into the storage area. in the 1.3mpixel there are 4 times more active lines than there are storage lines, so that active line one will be stored into storage line 1, active line 5 will be stored into storage line 2, active line 9 into storage line 3 and so on until finally active line 1045 will be stored into storage line 262. step 2: readout: during this step, the data in the storage area is transferred line by line into the horizontal regis- ter, from where it will be read out sequentially. by using this optically covered transfer area, there is still a minimum amount of smear in the low resolution mode. however, it is greatly reduced. this smear will only take place during the trans- fer time, because the pixels in the active area are constantly being exposed since the shutter is always open in the low resolution mode. this however is a small percentage of the total expo- sure. sensitivity: the sensitivity of the ccd to light can be increased by 2x or 3x in the ibm 2.0m with rgrg, gbgb bayer pattern. with a 2x extra sensitivity, twice as many photons will be accumulated. this mode can be used to increase resolution in low light scenes, and should be part of the agc/iris control loop. to achieve this extra sensitivity, 2 lines from the active area get added together into one line in the storage area. this is done by having an additional pulse on the s1 line (see figure 33). below are some examples: all of this can be programmed using register lowres_sen(25h). each bit of this register controls one pulse. the first pulse is always on. 0000 means only first pulse is on 1000 means the second and first pulse are on 0100 means the third and first pulse are on 0010 means the fourth and first pulse are on 0001 means the fifth and first pulse are on 0101 means the third, fifth and first pulse are on note that the user has to select very carefully the lines to be added. the selection of the lines is based on the color coating of the ccd. in some cases of color coating it is possible to add 2 lines, in other cases it is possible to add 3 lines (see below). (r = red pixel, b = blue pixel, g = green pixel) 3 lowres_sen2 2 lowres_sen1 1 lowres_sen0 bit mnemonic function
cs7620 46 ds301pp2 0 n_int8 exposure time in low resolution mode: number of lines of exposure during readout (262 = all readout). see register 26h for more details. bit mnemonic function (1) 0000 (1+3) 0100 (1+3+5) 0101 (1+5) 0001 1x 2x+ 3x+ 2x rgrgr gbgbg rgrgr gbgbg rgrgr (line 1) (line 5) (1) 0000 (1+4) 0010 1x 2x+ rgbrg gbrgb brgbr rgbrg gbrgb (line 1) (line 5) figure 29. 2 million pixel ibm ccd (5:1 reduction) figure 30. 2 million pixel ibm ccd (5:1 reduction) rgb pattern * note that in this mode the rgb pattern switches to rbg in the vertical direction. (1) 0000 (1+4) 0010 1x 2x+ rgbr gbrg brgb rgbr gbrg (line 1) (line 5) (1) 0000 (1+3) 0100 1x 2x rgrgrgrg gbgbgbgb rgrgrgrg gbgbgbgb rgrgrgrg (line 1) (line 8) line 1 line 2 line 1+ line 2+ (6) (6+8) gbgbgbgb rgrgrgrg gbgbgbgb figure 31. 1.3 million pixel ibm ccd (8:2 reduction) figure 32. 1.3 million pixel ibm ccd (4:1 reduction) rgb pattern optional lowres_sen3 optional lowres_sen2 optional lowres_sen1 optional lowres_sen0 v1 v2 v3 v4 s1 s2 s3 s4 tdv (20h) figure 33. vertical timing division for low resolution mode
cs7620 ds301pp2 47 4.28 timing control - lines of exposure in low resolution mode (msbs) default = 06h; read/write (address 26h) 4.29 timing control - polarity of vertical shift outputs default = ffh; read/write (address 28h) bit number 76543210 bit name n_int7 n_int6 n_int5 n_int4 n_int3 n_int2 n_int1 n_int0 default 00000110 bit mnemonic function 7n_int7 exposure time in low resolution mode: in low resolution mode, the cs7620 continuously outputs data on a frame by frame basis; so it can drive a lcd panel in a video mode. in this mode the cs7620 ignores the expose signal. n_int allows to shorten the exposure time while in low resolution mode. n_int controls the amount of time (measured in readout lines) where the ccd will be exposed to light. the default is 262, this means that the ccd receives full exposure during readout. by decreasing n_int, the amount of exposure can be decreased. to further increase this exposure time beyond the full 262 lines of readout time, the n_extra register (23h and 24h) is provided. 6n_int6 5n_int5 4n_int4 3n_int3 2n_int2 1n_int1 0n_int0 bit number 76543210 bit name v_polarity7 v_polarity6 v_polarity5 v_polarity4 v_polarity3 v_polarity2 v_polarity1 v_polarity0 default 11111111 bit mnemonic function 7 v_polarity7 vertical signal polarity: polarity of each of the eight vertical shift outputs (v1 v2 v3 v4 s1 s2 s3 s4), where v1 polarity = msb, s4 polarity = lsb a 0 indicates that the signal state is low, a 1 indicates that the signal state is high. 6 v_polarity6 5 v_polarity5 4 v_polarity4 3 v_polarity3 2 v_polarity2 1 v_polarity1 0 v_polarity0
cs7620 48 ds301pp2 4.30 horizontal timing control - h1 default = 68h; read/write (address 29h) bit number 76543210 bit name reserved h1d h1f_reg2 h1f_reg1 h1f_reg0 h1f_reg2 h1f_reg1 h1f_reg0 default - 1101000 bit mnemonic function 7- reserved 6h1d h1 default setting: during the vertical shift time, the horizontal clocks are held in one state. this bit controls whether h1 is held high or low during this time. a 0 indicates that the signal state is low, a 1 indicates that the signal state is high. 5 h1f_reg2 h1 falling edge: the phase of the falling edge of h1 can be programmed through this register. the falling edge of h1 corresponds to the rising edge of the internally selected clock. the phases of these clocks are shown in figure 19, with the complemented clocks being the inverse of these. 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 4 h1f_reg1 3 h1f_reg0 2 h1f_reg2 h1 rising edge: the phase of the rising edge of h1 can be programmed through this register. the rising edge of h1 corresponds to the rising edge of the internally selected clock. the phases of these clocks are shown in figure 19, with the complemented clocks being the inverse of these. 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 1 h1f_reg1 0 h1f_reg0
cs7620 ds301pp2 49 4.31 horizontal timing control - h2 default = 7ah; read/write (address 2ah) bit number 76543210 bit name reserved h2d h2f_reg2 h2f_reg1 h2g_reg0 h2g_reg2 h2g_reg1 h2g_reg0 default - 1111010 bit mnemonic function 7- reserved 6h2d h2 default setting: during the vertical shift time, the horizontal clocks are held in one state. this bit controls whether h2 is held high or low during this time. a 0 indicates that the signal state is low, a 1 indicates that the signal state is high. 5 h2f_reg2 h2 falling edge: the phase of the falling edge of h2 can be programmed through this register. the falling edge of h2 corresponds to the rising edge of the internally selected clock. the phases of these clocks are shown in figure 19, with the complemented clocks being the inverse of these. 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 4 h2f_reg1 3 h2g_reg0 2 h2g_reg2 h2 rising edge: the phase of the rising edge of h2 can be programmed through this register. the rising edge of h2 corresponds to the rising edge of the internally selected clock. the phases of these clocks are shown in figure 19, with the complemented clocks being the inverse of these. 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 1 h2g_reg1 0 h2g_reg0
cs7620 50 ds301pp2 4.32 horizontal timing control - h3 default = 4ch; read/write (address 2bh) bit number 76543210 bit name reserved h3d h3f_reg2 h3f_reg1 h3f_reg0 h3f_reg2 h3f_reg1 h3f_reg0 default - 1001100 bit mnemonic function 7- reserved 6h3d h3 default setting: during the vertical shift time, the horizontal clocks are held in one state. this bit controls whether h3 is held high or low during this time. a 0 indicates that the signal state is low, a 1 indicates that the signal state is high. 5 h3f_reg2 h3 falling edge: the phase of the falling edge of h3 can be programmed through this register. the falling edge of h3 corresponds to the rising edge of the internally selected clock. the phases of these clocks are shown in figure 19, with the complemented clocks being the inverse of these. 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 4 h3f_reg1 3 h3f_reg0 2 h3f_reg2 h3 rising edge: the phase of the rising edge of h3 can be programmed through this register. the rising edge of h3 corresponds to the rising edge of the internally selected clock. the phases of these clocks are shown in figure 19, with the complemented clocks being the inverse of these. 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 1 h3f_reg1 0 h3f_reg0
cs7620 ds301pp2 51 4.33 horizontal timing control - h4 default = 1eh; read/write (address 2ch) bit number 76543210 bit name reserved h4d h4f_reg2 h4f_reg1 h4f_reg0 h4f_reg2 h4f_reg1 h4f_reg0 default - 0011110 bit mnemonic function 7- reserved 6h4d during the vertical shift time, the horizontal clocks are held in one state. this bit controls whether h4 is held high or low during this time. a 0 indicates that the signal state is low, a 1 indicates that the signal state is high. 5 h4f_reg2 the phase of the falling edge of h4 can be programmed through this register. the falling edge of h4 corresponds to the rising edge of the internally selected clock. the phases of these clocks in shown in figure 19, with the complement- ed clocks being the inverse of these (i.e. the falling edge of p1 is the rising edge of p1 , etc.). 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 4 h4f_reg1 3 h4f_reg0 2 h4f_reg2 the phase of the rising edge of h4 can be programmed through this register. the rising edge of h4 corresponds to the rising edge of the internally selected clock. the phases of these clocks in shown are figure 19, with the comple- mented clocks being the inverse of these. 0 = t0 1 = t1 2 = t2 3 = t3 4 = t4 5 = t5 6 = t6 7 = t7 (see figure 19) 1 h4f_reg1 0 h4f_reg0
cs7620 52 ds301pp2 4.34 horizontal timing control - analog delays default = 00h; read/write (address 2dh) bit number 76543210 bit name resrved phase_h1 phase_h0 rgf_reg1 rgf_reg0 rgr_reg1 rgr_reg0 default -- 000000 bit mnemonic function 7:6 - reserved 5 phase_h1 phase shift of h1-h4 pulses: this register allows for minor shifts in the phases of h1-h4. this can help to optimize the sampling time of the ccd in- put signal. 1 unit of delay is ~1.5 ns. this should be used for final adjustments only, with large adjustments done through the selection of the appropriate clock phases for each edge. all four horizontal clocks shift together when this register is used. 0 - no shift 1 - 1.5 ns shift 2 - 3.0 ns shift 3 - 4.5 ns shift 4 phase_h0 3 rgf_reg1 rg falling edge phase shift: this register allows for minor shifts in the phase of the falling edge of rg. 1 unit of delay is ~1.5 ns. 0 - no shift 1 - 1.5 ns shift 2 - 3.0 ns shift 3 - 4.5 ns shift 2 rgf_reg0 1 rgr_reg1 rg rising edge phase shift: this register allows for minor shifts in the phase of the rising edge of rg. 1 unit of delay is ~1.5 ns. 0 - no shift 1 - 1.5 ns shift 2 - 3.0 ns shift 3 - 4.5 ns shift 0 rgr_reg0
cs7620 ds301pp2 53 4.35 compander - black slope, slopes (msbs) default = 00h; read/write (address 2eh) 4.36 compander - slope 1 (lsbs) default = a8h; read/write (address 2fh) bit number 76543210 bit name reserved comp_linear slope18 slope28 slope38 slope48 default --- 00000 bit mnemonic function 7:5 - reserved 4 comp_linear compander black level slope: 0 - the values of 0 to 64 in a 13 bit rep- resentation are set to offset1 in a 10 bit representation. offset1 can be set in register 33h. 1 - in this case the black level is mapped linearly from 13 bit values to 10 bit values. 64 is mapped into 8. all the other values between 0 and 64 are divided by 8 in order to get the 10 bit representation. (see figure 13) 3 slope18 compander slope 1: msb of slope of first segment of companding curve. (see figure 13) 2 slope28 compander slope 2: msb of slope of second segment of companding curve. (see figure 13) 1 slope38 compander slope 3: msb of slope of third segment of companding curve. (see figure 13) 0 slope48 compander slope 4: msb of slope of fourth segment of companding curve. (see figure 13) bit number 76543210 bit name slope17 slope16 slope15 slope14 slope13 slope12 slope11 slope10 default 10101000 bit mnemonic function 7 slope17 compander slope1: slope of first segment (slope1[8:0]) of companding curve. max value is 1.996. the lsb step size is 0.0039. (see figure 13) 6 slope16 5 slope15 4 slope14 3 slope13 2 slope12 1slope11 0 slope10
cs7620 54 ds301pp2 4.37 compander - slope 2 (lsbs) default = 60h; read/write (address 30h) 4.38 compander - slope 3 (lsbs) default = 20h; read/write (address 31h) bit number 76543210 bit name slope27 slope26 slope25 slope24 slope23 slope22 slope21 slope20 default 01100000 bit mnemonic function 7 slope27 compander slope 2: slope of second segment (slope2[8:0]) of companding curve. max value is 1.996. the lsb step size is 0.0039. (see figure 13) 6 slope26 5 slope25 4 slope24 3 slope23 2 slope22 1 slope21 0 slope20 bit number 76543210 bit name slope37 slope36 slope35 slope34 slope33 slope32 slope31 slope30 default 00100000 bit mnemonic function 7 slope37 compander slope 3: slope of third segment (slope3[8:0]) of companding curve. max value is 1.996. the lsb step size is 0.0039. (see figure 13) 6 slope36 5 slope35 4 slope34 3 slope33 2 slope32 1 slope31 0 slope30
cs7620 ds301pp2 55 4.39 compander - slope 4 (lsbs) default = 07h; read/write (address 32h) 4.40 compander - offset 1 default = 08h; read/write (address 33h) bit number 76543210 bit name slope47 slope46 slope45 slope44 slope43 slope42 slope41 slope40 default 00000111 bit mnemonic function 7 slope47 compander slope 4: slope of fourth segment (slope4[8:0]) of companding curve. max value is 1.996. the lsb step size is 0.0039. (see figure 13) 6 slope46 5 slope45 4 slope44 3 slope43 2 slope42 1 slope41 0 slope40 bit number 76543210 bit name offset17 offset16 offset15 offset14 offset13 offset12 offset11 offset10 default 00001000 bit mnemonic function 7 offset17 compander offset 1: black level value of companding curve if not in linear mapping mode (comp_linear = 0). (see figure 13) 6 offset16 5 offset15 4 offset14 3 offset13 2 offset12 1 offset11 0 offset10
cs7620 56 ds301pp2 4.41 compander - offsets (msbs) default = 0bh; read/write (address 34h) 4.42 compander - offset 2 (lsbs) default = bfh; read/write (address 35h) bit number 76543210 bit name reserved offset29 offset28 offset39 offset38 offset49 offset48 default -- 001011 bit mnemonic function 7:6 - reserved 5 offset29 compander offset 2: msbs of offset of second segment of companding curve. (see figure 13) 4 offset28 3 offset39 compander offset 3: msbs of offset of third segment of companding curve. (see figure 13) 2 offset38 1 offset49 compander offset 4: msbs of offset of fourth segment of companding curve. (see figure 13) 0 offset48 bit number 76543210 bit name offset27 offset26 offset25 offset24 offset23 offset22 offset21 offset 20 default 10111111 bit mnemonic function 7offset 27 compander offset 2: offset of second segment (offset2[9:0]) of companding curve. (see figure 13) 6 offset26 5 offset25 4 offset24 3 offset23 2 offset22 1 offset21 0 offset20
cs7620 ds301pp2 57 4.43 compander - offset 3 (lsbs) default = 05h; read/write (address 36h) 4.44 compander - offset 4 (lsbs) default = 20h; read/write (address 37h) bit number 76543210 bit name offset37 offset36 offset35 offset34 offset33 offset32 offset31 offset30 default 00000101 bit mnemonic function 7 offset37 compander offset 3: offset of third segment (offset3[9:0]) of companding curve. (see figure 13) 6 offset36 5 offset35 4 offset34 3 offset33 2 offset32 1 offset31 0 offset30 bit number 76543210 bit name offset47 offset46 offset45 offset44 offset43 offset42 offset41 offset40 default 00100000 bit mnemonic function 7 offset47 compander offset 4: offset of fourth segment (offset4[9:0]) of companding curve. (see figure 13) 6 offset46 5 offset45 4 offset44 3 offset43 2 offset42 1 offset41 0 offset40
cs7620 58 ds301pp2 4.45 compander - x1 (msbs) default = 03h; read/write (address 38h) 4.46 compander - x1 (lsbs) default = 20; read/write (address 39h) bit number 76543210 bit name reserved x112 x111 x110 x19 x18 default --- 00011 bit mnemonic function 7:5 - reserved 4x112 compander x1: end value of first segment of companding curve (msbs). (see figure 13) 3 x111 2x110 1x19 0x18 bit number 76543210 bit name x17 x16 x15 x14 x13 x12 x11 x10 default 00100000 bit mnemonic function 7x17 compander x1: end value of first segment (x1[12:0]) of companding curve (lsbs). (see figure 13) 6x16 5x15 4x14 3x13 2x12 1x11 0x10
cs7620 ds301pp2 59 4.47 compander - x2 (msbs) default = 05h; read/write (address 3ah) 4.48 compander - x2 (lsbs) default = 18h; read/write (address 3bh) bit number 76543210 bit name reserved x212 x211 x210 x29 x28 default --- 00101 bit mnemonic function 7:5 - reserved 4 x212 compander x2: end value of second segment of companding curve (msbs). (see figure 13) 3x211 2 x210 1x29 0x28 bit number 76543210 bit name x27 x26 x25 x24 x23 x22 x21 x20 default 00011000 bit mnemonic function 7x27 compander x2: end value of second segment (x2[12:0]) of companding curve (lsbs). (see figure 13) 6x26 5x25 4x24 3x23 2x22 1x21 0x20
cs7620 60 ds301pp2 4.49 compander - x3 (msbs) default = 0bh; read/write (address 3ch) 4.50 compander - x3 (lsbs) default = 58h; read/write (address 3dh) bit number 76543210 bit name reserved x312 x311 x310 x39 x38 default --- 01011 bit mnemonic function 7:5 - reserved 4 x312 compander x3: end value of third segment of companding curve (msbs). (see figure 13) 3x311 2 x310 1x39 0x38 bit number 76543210 bit name x37 x36 x35 x34 x33 x32 x31 x30 default 01011000 bit mnemonic function 7x37 compander x3: end value of third segment (x3[12:0]) of companding curve (lsbs). (see figure 13) 6x36 5x35 4x34 3x33 2x32 1x31 0x30
cs7620 ds301pp2 61 4.51 power_up counter default = 7dh; read/write (address 3dh) 4.52 valid_data/dout edge/clock_in divider default = 01h; read/write (address 3fh) bit number 76543210 bit name cnt_reg7 cnt_reg6 cnt_reg5 cnt_reg4 cnt_reg3 cnt_reg2 cnt_reg1 cnt_reg0 default 01111101 bit mnemonic function 7 cnt_reg7 power up counter register: when coming out of power down, there is a pe- riod of time required for voltages and currents to settle to the proper values, for the pll to lock, and for the gain calibration to be performed. this should all be accomplished within 500 s. the pixel clocks required to meet this 500 s time should be programmed into this register. note that if the master clock is being divided on chip, the dividers output clock is the pixel clock. 6 cnt_reg6 5 cnt_reg5 4 cnt_reg4 3 cnt_reg3 2 cnt_reg2 1 cnt_reg1 0 cnt_reg0 bit number 76543210 bit name reserved valid_data dout_edge clk_divide4 clk_divide3 clk_divide2 clk_divide1 clk_divide0 default - 0000001 bit mnemonic function 7- reserved 6 valid_data valide data mode: this mode will redefine the clko pin as a data valid pin. the data_valid signal will only toggle over active pixels and is phase-aligned with the master clock. the user may then latch the data during this valid time using the master clock or a clock derived from it. note that this mode may only be used if the master clock frequency is an integer multiple greater than 1 of the pixel rate (see figures 14 and 15). if this mode is not selected, the output clock is output on the clko pin. 0 - digital clock output on clko pin 1 - valid_data signal on clko pin 5 dout_edge dout edge selelction: if valid_data = 0, the edge of the clock that clocks out the data is selected by this bit. the data may be output either on the rising or the falling edge of the output clock, clko. hsync and rd_out are also out- put on same edge. note that if valid_data = 1, this register is invalid. * hsync and rd_out also output on the same edge
cs7620 62 ds301pp2 4.53 dac #1 control default = 00h; read/write (address 40h) 4.54 dac #2 control default = 00h; read/write (address 41h) 4 clk_divide4 clock divider: the master clock frequency can be an integer multiple of the pixel clock rate. this register contains the number by which to divide the mas- ter clock frequency in order to get the pixel clock frequency. if a 0 is pro- grammed here, the divider is bypassed and the master clock is assumed to be at the pixel rate. 3 clk_divide3 2 clk_divide2 1 clk_divide1 0 clk_divide0 bit number 76543210 bit name dac_cntl17 dac_cntl16 dac_cntl15 dac_cntl14 dac_cntl13 dac_cntl12 dac_cntl11 dac_cntl10 default 00000000 bit mnemonic function 7 dac_cntl17 dac#1 control: this is the digital input code to the general purpose dac#1 which will then be converted into the analog current output. each lsb in this word will increment the output by ~8.7 a in low current mode and ~34 a in high current mode. 6 dac_cntl16 5 dac_cntl15 4 dac_cntl14 3 dac_cntl13 2 dac_cntl12 1 dac_cntl11 0 dac_cntl10 bit number 76543210 bit name dac_cntl27 dac_cntl26 dac_cntl25 dac_cntl24 dac_cntl23 dac_cntl22 dac_cntl21 dac_cntl20 default 00000000 bit mnemonic function 7 dac_cntl27 dac #2 control: this is the digital input code to the general purpose dac#2 which will then be converted into the analog current output. each lsb in this word will increment the output by ~8.7 a in low current mode and ~34 a in high current mode. 6 dac_cntl26 5 dac_cntl25 4 dac_cntl24 3 dac_cntl23 2 dac_cntl22 1 dac_cntl21 0 dac_cntl20 bit mnemonic function
cs7620 ds301pp2 63 4.55 device id default = ech; read (address 7eh) 4.56 rev code default = 02h; read (address 7fh) bit number 76543210 bit name devide_id7 devide_id6 devide_id5 devide_id4 devide_id3 devide_id2 devide_id1 devide_id0 default 11101100 bit mnemonic function 7devide_id7 device id: this read-only register is the unique id for the cs7620. 6devide_id6 5devide_id5 4devide_id4 3devide_id3 2devide_id2 1devide_id1 0devide_id0 bit number 76543210 bit name rev_code7 rev_code6 rev_code5 rev_code4 rev_code3 rev_code2 rev_code1 rev_code0 default 00000010 bit mnemonic function 7 rev_code7 revision code: this read-only register is the revision code for the cs7620. 6 rev_code6 5 rev_code5 4 rev_code4 3 rev_code3 2 rev_code2 1 rev_code1 0 rev_code0
cs7620 64 ds301pp2 5 pin descriptions dout3 dout2 dout1 dout0 clko v4 v3 v2 v1 s4 s3 s2 s1 clock_in n/c gnda2 vdda2 bypass_pll rst rg h1 h2 h3 h4 vdda3 gnda3 diag1 diag0 ref_capp ref_capn n/c vdda1 41 43 45 47 33 35 37 39 7 5 3 1 15 13 11 9 dout4 dout5 dout6 dout7 rd_out expose pwr_dn test scan_mode dac_out1 dac_out2 n/c sen gnd_ring vdd_ring hsync vddd sclk sdati sdato dout12 clamp line_ena gndd dout8 dout9 dout10 dout11 bg_res n/c ain gnda1 17 19 21 23 25 27 29 31 63 61 59 57 55 53 51 49 8 6 4 2 16 14 12 10 18 20 22 24 26 28 30 32 42 44 46 48 34 36 38 40 64 62 60 58 56 54 52 50 64-pin tqfp top view
cs7620 ds301pp2 65 5.1 supply vdda[1:2] - supply for analog pins 25 and 40 5 v analog supply. vdda3 - supply for horizontal outputs pin 32 3.3 v or 5 v analog supply. vddd - supply for digital pin 5 5 v digital supply. vdd_ring - supply for pad ring (digital pads) pin 11 3.3 v or 5 v digital supply 5.2 ground gnda[1:2] - ground for analog pins 24 and 41 gnda1 and gnda2 are supplied by vdda1 and vdda2 respectively. gnda3 - ground for horizontal outputs pin 31 supplied by vdda3. gndd - ground for digital pin 4 supplied by vddd. gnd_ring - ground for pad ring (digital pads) pin 10 supplied by vdd_ring. 5.3 cmos input bypass_pll - powers down pll if not in use pin 39 supplied by vdda2. clamp - black level clamp signal pin 2 only used if an external timing generator is used. supplied by vdd_ring. clock_in - chip input clock pin 43 supplied by vdda2. expose - begin expose sequence pin 14 expose signal from the shutter. supplied by vdd_ring. line_ena - line enable signal pin 3 supplied by vdd_ring. pwr_dn - places chip in full power down pin 15 supplied by vdd_ring. ref_capn - reference capacitor- negative terminal pin 27 supplied by vdda1. a 1 f ceramic capacitor should be connected between ref_capn and ref_capp. ref_capp - reference capacitor- positive terminal pin 28 supplied by vdda1. a 1 f ceramic capacitor should be connected between ref_capn and ref_capp.
cs7620 66 ds301pp2 rst - reset pin, negative true pin 38 may be connected to external power-on-reset-circuit. supplied by vdda2. scan_mode - test pin 17 supplied by vdd_ring. sclk - serial bus clock signal pin 6 supplied by vdd_ring. sdati - serial bus data input signal pin 7 supplied by vdd_ring. sen - serial bus enable signal-chip select (active low) pin 9 supplied by vdd_ring. test - test enable pin pin 16 supplied by vdd_ring. 5.4 cmos analog input ain - video data input from ccd pin 23 supplied by vdda1. bg_res - band-gap resistor pin 21 supplied by vdda1. a 10 k w resistor should be connected between bg_res and gnda1. 5.5 cmos analog output dac_out[1:2] - general purpose digital-to-analog converter output pins 18 and 19 supplied by vdda1. 5.6 cmos 4 ma output clko - clock = output pin 52 signal on this pin can either be the pixel clock output or data_valid signal out- put. supplied by vdd_ring. dout[0:12] - digitized ccd data output pins 53-64, and 1 dout0 is lsb. supplied by vdd_ring. sdato - serial bus data output signal pin 8 supplied by vdd_ring. hsync - horiz sync (active low) pin 12 supplied by vdd_ring. rd_out - readout signal (active low) pin 13 supplied by vdd_ring. rg - reset gate clock pulse for ccd pin 37 supplied by vdda3.
cs7620 ds301pp2 67 s[1:4] - storage timing signal pins 44-47 supplied by vdda2. v[1:4] - vertical timing signal pins 48-51 supplied by vdda2. 5.7 cmos 28 ma output h[1:4] - horz. shift reg clock to ccd pins 36, 35, 34, and 33 supplied by vdda3. 5.8 misc diag[0:1] - cmos analog test pins pins 29 and 30 test pins only - nc. supplied by vdda1. n/c - no connect pins 20, 22, and 26 n/c - no connect pin 42
cs7620 68 ds301pp2 6 package dimensions inches millimeters dim min max min max a --- 0.063 --- 1.60 a1 0.002 0.006 0.05 0.15 b 0.007 0.011 0.17 0.27 d 0.461 0.484 11.70 12.30 d1 0.390 0.398 9.90 10.10 e 0.461 0.484 11.70 12.30 e1 0.390 0.398 9.90 10.10 e* 0.016 0.024 0.40 0.60 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 64l tqfp package drawing e1 e d1 d 1 e l b a1 a
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